Home of Quality & Flexibility
We are a team of experienced designers with over 20 years of collaborative experience. Our focus is on delivering high-quality solutions, and we take pride in our adaptability to cater to our clients’ unique requirements. If you are looking for digital design services for ASIC/FPGA, we have a team of creative and experienced engineers dedicated to fulfilling your specific demands. Welcome to Silesia Devices!
Silesia Devices in numbers
We pride ourselves on the exceptional quality and reach of our products and services. To give you an idea of just how far our impact extends, here are some key figures.
10 years on the market
Silesia Devices has been on the market for 10 years, providing high-quality products and services to our customers.
doubled in size
As a result of the steady annual growth of the company our team has more than doubled in size.
Global client reach
High-quality services and a well-established reputation have resulted in acquiring customers from 22 countries around the globe.
Since Silesia Devices was founded we
Silesia Devices offers state-of-the-art ASIC/FPGA design services, ranging from simple inter-circuit communication devices to complex legacy chip replacements.
The highly featured sub-only core communicates in Single Data Rate (SDR) mode, but can tolerate High Data Rate (HDR) traffic. It can coexist and communicate with legacy I2C devices, and it can optionally be configured to operate as such in an I3C or I2C bus. The I3C-S needs no firmware support to parse and execute the broadcast or direct Common Command Codes (CCCs) relevant to I3C Basic Sub. It can be assigned a Dynamic Address by the bus main, or use its legacy I2C static address, it supports Hot Join and is capable of generating In-Band Interrupts when directed by the host to do so.
Designed for easy integration, the I3C-S can operate with private I3C or I2C read / write transfers utilizing a FIFO available to the host via an APB Sub interface. Alternatively, the core can operate in I3C-to-AHB bridging mode, where it autonomously converts private I3C or legacy I2C transfers to accesses on its AHB main port using a simple yet configurable over-I3C protocol.
The highly flexible core offers synthesis-time and run-time configuration options, which allow adapting its size and behavior to the application requirements.
The SPMI-CTRL core supports the latest version (v2.0) of the MIPI-SPMI specification, and is suitable for the implementation of either main or sub nodes in an SPMI bus. The core is designed to minimize the software load on the host processor. Once configured, the core requires no assistance from the host to initialize the bus, connect to bus or disconnect from the bus, grant access of the bus, execute incoming SPMI commands, generate ACK/NACK responses, and check address and data parity. Although the core only expects the host to provide the outgoing SPMI commands, it provides thorough status information to the host, which can be used for a higher application layer or for debugging purposes.
Integration of the core is extremely simple: The core provides access to its registers via a AMBA™2 APB completer interface, and converts the incoming SPMI read/write commands to accesses on its AHB main port. This SPMI-AHB bridging allows easy mapping of the SPMI address space to shared memories or peripheral registers. A dedicated interface allows integration with application specific authentication logic, which can be reduced to just hardwiring the authentication response data.
The CACHE-CTRL IP core is a flexible cache memory controller providing a 32-bit AHB subordinate processor interface and a 32-bit AHB manager interface to the memory subsystem.
The cache controller core supports a four-way associative cache memory, and implements a Least Recently Used (LRU) replacement policy. The number of cache lines and the cache line width are configurable at synthesis time. The core only caches read accesses and invalidates the cached data if a write access to a cached memory location occurs.
Mapping the cache controller to any technology is straightforward, as the core does not require any special type of SRAM modules, only using standard, single-ported SRAMs. Furthermore, the design is scan-ready as it uses only rising-edge triggered flip-flops and contains no internal tri-states. Integration of the core is trouble-free, as the core uses standard 32-bit AHB interfaces, and supports clock gating.
The CACHE-CTRL core has been robustly verified and is silicon-proven.
The T80251XC3 core implements a compact 16-bit microcontroller that executes the MCS®251 & MCS®51 instruction sets and includes a configurable range of features and integrated peripherals. The core’s advanced architectural design enables a high-performance 8051/80251-compatible MCU in a relatively small silicon footprint. The CPU itself (including the register files) is smaller than 13,000 gates, and can deliver 0.1455 DMIPS/MHz.
The T80251XC3 is extremely energy efficient, especially for applications that process 8- or 16-bit data. Its small footprint translates to very little power leakage, and its better performance than other 8-bit or 16-bit MCUs allows clocking at lower frequencies. Users can also adjust the core’s energy consumption to match the processing workload via dynamic frequency scaling and independent control of the CPU and peripherals clocks. Finally, the 80251 ISA’s complex addressing modes minimize the number of load/store operations, which typically comprise 20% or more of a RISC processor’s code. With denser code needing smaller firmware memory and fewer required memory accesses, the energy consumption of the MCU’s memory subsystem can be significantly less with the T80251XC3.
The core has a rich set of optional features and pre-integrated peripherals, allowing function, performance, and area to be balanced for each specific application. Software development is facilitated by a single-wire or JTAG debugging interface that operates seamlessly within the ARM® Keil® C251 integrated development environment. Inexpensive debug pods and a complete reference design board package are available.
The T8051XC3 core implements one of the smallest-available 8-bit MCS®51-compatible microcontrollers. The core integrates an 8051 CPU with a serial communication controller, flexible timer/counter, multi-purpose I/O port, interrupt controller, and optionally with a debug unit supporting JTAG and Single-Wire interfaces. The MCU with all peripherals uses as little as 6.6K gates in an ASIC implementation.
The MCU executes some 8051 instructions in a single clock cycle, thus providing 0.1236 DMIPS/MHz (Dhrystone 2.1 benchmark score). Furthermore, the core can run at frequencies over 450 MHz on a 90nm technology, offering performance that is more than 300x that of the original 8051.
The T8051XC3 runs the legacy code of existing systems, but is also ready for highly productive new software development. This is facilitated through the on-chip debugging option, and debug pods that cooperate with the Keil µVision C51 and IAR Embedded Workbench for 8051 IDEs.
The S80251XC3 is a synthesizable soft HDL core of a super-fast 16-bit 80C251-compatible microcontroller, backward compatible with the most popular 8-bit microcontroller, the 8051. It runs 69.7 times faster than the original 8051 chip (measured by Dhrystone benchmark), making it the highest performance MCS®51 instruction set compatible IP core available at the time of its release.
The new S80251XC3 uses a Harvard architecture with separate instruction and data buses, branch prediction, branch target caches, and stacking/unstacking speed-up features, and is even able to execute some instructions in parallel. With the rich set of peripherals and options, including timers and counters, buses and interfaces, the new core is an excellent choice as a sensor or peripheral subsystem controller in mobile, Internet of Things (IoT), and industrial systems, or as a main embedded processor in mixed-signal ICs for a variety of applications.
The S8051XC3 is a synthesizable soft HDL core of a super fast 8-bit microcontroller compatible with the world’s most popular 8051 architecture. It offers the highest performance, low-energy and a configurable range of features and integrated peripherals.
At the time of its release, it is the fastest 8051-compatible 8-bit MCU ever designed. Running with a single clock per machine cycle, requiring an average of 1.5 to 1.8 machine cycles per instruction (depending on configuration), it delivers from 9.41 to 26.85 times the performance of the original 8051 at the same frequency (measured with Dhrystone 2.1 benchmark), without requiring an external arithmetic acceleration unit (such as an MDU).
Most of the extensions can be individually enabled or disabled from implementation, allowing to reduce the die size when top performance is not required. The core includes all typical 8051 peripherals like Timers, PWM, UART, SPI, I2C and extremely short latency interrupt system with extended priority structure.
We are a company open to research collaboration and inter-corporate cooperation
Silesia Devices with two other companies from Switzerland and Germany have carried out a joint research and development project under the Eurostars programme, which aims to support innovative small and medium-sized enterprises.
The project is called ‘Tell multiple stories with a single camera – leveraging AI and FPGAs for 4x real-time cinematography’, better known by its abbreviated name FlysEyes, and it focuses on developing a device that allows up to four independent shots from a single high-quality camera.
Each shot, called a region of interest (ROI), is an image extraction from the same camera. The control of the frame is done by software using artificial intelligence and real-time cinematic planning algorithms. The device allows independent channels to be derived for each shot.
The technology has many potential applications in the film, TV and streaming industries, as it saves time and production costs and provides greater flexibility and creativity in scene creation.
In this project, Silesia Devices was responsible for designing and commissioning the hardware layer for processing, extracting and encoding the video stream using an FPGA chip. Seervision provided the software and algorithms to control the shots. Satis&Fy handled the prototype testing and performance evaluation under production conditions.
Silesia Devices designed an electronic device in a 1U RACK case, based on an FPGA chip, which processes the corresponding video stream in real-time, dividing it into 4 different ROIs, simultaneously encoding the basic and obtained streams, sending them over a standard Ethernet link and receiving configuration and positioning information of the extracted streams on the fly. The developed technology has been tested and implemented in the prototype project under real conditions, i.e. the reality of a TV studio.
The project, initiated in September 2020 with a budget of approximately €1 million, received support from various entities including the National Centre for Research and Development (NCBR) in Poland.
Key product features
Need help with digital design? Our agile team of experts is here to provide top-notch consultancy services tailored to your changing needs.
Our team possesses the flexibility to adapt to your evolving requirements. We provide consultancy services in digital design and are happy to share the knowledge of experienced designers. We are available to provide you with reliable expertise and support.
- Design of end-of-life chips replacements
- Custom microprocessors, microcontrollers, DSP
- Hardwired DSP
- Peripheral devices
- Design, integration & verification of silicon IP on demand
At our core, we prioritize your needs and aim to provide practical solutions that are both innovative and efficient, precisely tailored to your requirements. Our comprehensive consultancy services cover everything from the initial design phase to seamless integration, thorough verification, and rigorous testing.
If you’re searching for a partner well-versed in digital design, backed by knowledge and experience, and dedicated to offering dependable support and creative solutions, we are the team you can rely on. Get in touch with us today to start a conversation about your specific needs, and together we can explore how we can help bring your projects to life.
Our goal is to establish a workplace that promotes fairness, friendliness, creativity, high-quality output, and work-life balance.
Silesia Devices was established in 2013 as a response to the consolidation of the Silicon IP market. Our journey began in the late 2000s with the desire to create a fair and friendly workplace that supports creativity, provides high-quality products and services, while embracing the idea of work life balance.
Thanks to the support of CAST, Inc., we have established ourselves as a dependable and innovative company, setting ourselves apart from larger corporations by leveraging our creative and agile approach to problem-solving and responding to the diverse needs of our clients. Our team, managed by engineers, has over 50 years of combined experience.
Over the past decade, we have accomplished significant milestones including the sale of over 160 licenses, completion of 10 design service contracts, establishment of 5 major product lines, participation in 1 international, EU-financed project, and doubling our team size. We have worked with partners and customers from 22 countries, and strengthened ties with our strategic partner CAST, Inc.
Maciej Pyka is the President of Silesia Devices. He graduated with an MSEE from the Silesian University of Technology in 2000 and has since worked extensively in digital semiconductor IP design and verification. He led a team of MCU group at a company later acquired by Cadence and spent several months providing on-site design services at one of Europe’s leading mixed-signal IC manufacturers. He has developed several FPGA-based systems from start to finish and possesses expertise in digital IC design, verification, PCB, and embedded C. He specializes in microprocessors, DSP, and raw video. Since 2013, he has successfully co-run Silesia Devices.
In his free time, he enjoys DIY projects, cooking, and traveling.
Jacek Tymiński, Vice President of Silesia Devices, has had a lifelong passion for electronics. He earned his MSEE from Gliwice University of Technology in 2001, specializing in IP design and verification with a focus on microcontrollers and serial ports. For the past decade, he has co-owned and co-managed Silesia Devices while also participating in interdisciplinary commercial and social projects. He enjoys expanding his knowledge and expertise in various fields, even outside of business pursuits.
In his free time, he finds relaxation in moments of complete silence or through physical activities and gardening.
Silesia Devices has formed a strategic partnership with CAST, Inc.
CAST develops, aggregates, integrates, markets, and supports semiconductor intellectual property in the form of reusable IP cores and subsystems. An IP market driver since 1993, CAST today focuses on providing uniquely-effective solutions for specific SoC design and application challenges, including the best available 8051 microcontrollers.
Flexible, royalty-free licensing makes these products extremely cost-effective, while stringent standards fine-tuned over hundreds of successful customer projects ensure their easy integration and use.
The likelihood of choosing and using IP improperly is decreased to almost nothing by working with CAST’s sales and support team, which is arguably among the most experienced in the market.
Visit the company website to learn more and see CASTs complete line of IP cores and subsystems, which also features 32-bit processors; video and image compression; and peripheral, graphics processing, encryption, interface and other essential system IP.
CAST was founded in 1993 and has always focused on reusable IP cores. We have helped thousands of companies worldwide gain a competitive edge, and they have built our IP into billions of shipping product units. One-third of our sales are to repeat customers.
Silesia Devices strives to create a fair and friendly workplace that fosters creativity, delivers high-quality products and services, and promotes work-life balance.
Currently, the internship program is closed. The next opportunity to participate in an internship at Silesia Devices will be available in the summer of 2024.
Our internship offer is primarily dedicated to students of the Department of Automation, Electronics, and Computer Science. However, we will welcome anyone with an interest in hardware description languages (HDL) design.
During the internship, interns will work closely with their mentor and actively participate in the implementation of ongoing projects. They will also have the opportunity to undertake training projects, providing them with a comprehensive understanding of the practical aspects of the design process. Moreover, interns may have the chance to incorporate the practical part of their thesis into the internship program.
Upon successful completion of the internship, selected students will be considered for employment opportunities.
What will you be doing?
Our 12-week internship program offers you a unique opportunity to join one of our dynamic design teams, where you will collaborate with and learn from experienced professionals. Throughout the program, you will acquire a solid foundation in both the theoretical and practical aspects of digital integrated circuit design and verification, utilizing hardware description languages (HDL).
As an intern, you will have hands-on experience with simulation and analysis tools, allowing you to optimize semiconductor parameters and maintain essential technical documentation. Each day, you will actively participate in the design, construction, and verification of our cutting-edge products, benefiting from strategic collaborations with international partners, which provide access to licensed tools and systems.
In addition to technical involvement, you will also be engaged in project meetings, gaining exposure to agile management methodologies employed within our organization. This exposure will facilitate rapid familiarization with your colleagues, the organizational structure, and its operations.
By participating in our internship program, you will gain valuable practical skills, expand your knowledge in integrated circuit design, and establish meaningful connections within the industry.
What are our requirements?
- Student status, preferably at least in their 3rd year of study.
- Basic knowledge of electronics, with a focus on digital circuits.
- Proficiency in computer software used for digital circuit design and simulation, as well as familiarity with HDL languages (Hardware Description Languages).
- Skills in low-level (embedded) software development using C would be a plus.
- Strong command of both English and Polish languages is welcome.
- Demonstrated interest in emerging semiconductor technologies and innovative solutions.
- Creative thinking, analytical skills, and the ability to work effectively in a team.
We’re looking for a skilled ASIC and FPGA designer who can create intricate and innovative architectures and develop solutions for challenging problems. This position is available in Katowice, Poland, in hybrid work model.
- Oversee the development of ASIC blocks and subsystems (which may involve FPGAs) from idea to final productization.
- Develop and execute integration, bring-up, and test plans.
- Create detailed and comprehensive internal specifications.
- Implement designs in RTL and evaluate synthesis outcomes for cost and performance.
- Work in small, dynamic teams for subprojects and customer support.
- Provide mentorship to junior team members.
- At least three years of relevant experience.
- Bachelor’s or master’s degree in Electrical or Computer Engineering or compensating experience.
- Demonstrated success in developing complex ASICs and FPGAs.
- Proven ability to design major blocks involving ASIC, IPs, logic, and FPGAs.
- Fluent in English, at least basic knowladge of Polish is a plus.
- Ability to work in a team.
Do you have any questions? Need support? Get in touch with us!
Address: ul. Panewnicka 22, 40-709 Katowice, Poland