I3C_S, The MIPI Improved Inter-Integrated Circuit Bus Basic Slave Controller Core
The highly featured slave-only core communicates in Single Data Rate (SDR) mode, but can tolerate High Data Rate (HDR) traffic. It can coexist and communicate with legacy I2C devices, and it can optionally be configured to operate as such in an I3C or I2C bus. The I3C-S needs no firmware support to parse and execute the broadcast or direct Common Command Codes (CCCs) relevant to I3C Basic Slaves. It can be assigned a Dynamic Address by the bus master, or use its legacy I2C static address, it supports Hot Join and is capable of generating In-Band Interrupts when directed by the host to do so.
Designed for easy integration, the I3C-S can operate with private I3C or I2C read / write transfers utilizing a FIFO available to the host via an APB Slave interface. Alternatively, the core can operate in I3C-to-AHB bridging mode, where it autonomously converts private I3C or legacy I2C transfers to accesses on its AHB master port using a simple yet configurable over-I3C protocol.
The highly flexible core offers synthesis-time and run-time configuration options, which allow adapting its size and behavior to the application requirements.
SPMI_CTRL, The MIPI System Power Management Interface Controller Core
The SPMI-CTRL core supports the latest version (v2.0) of the MIPI-SPMI specification, and is suitable for the implementation of either master or slave nodes in an SPMI bus. The core is designed to minimize the software load on the host processor. Once configured, the core requires no assistance from the host to initialize the bus, connect to bus or disconnect from the bus, grant access of the bus, execute incoming SPMI commands, generate ACK/NACK responses, and check address and data parity. Although the core only expects the host to provide the outgoing SPMI commands, it provides thorough status information to the host, which can be used for a higher application layer or for debugging purposes.
Integration of the core is extremely simple: The core provides access to its registers via a AMBA™2 APB slave interface, and converts the incoming SPMI read/write commands to accesses on its AHB master port. This SPMI-AHB bridging allows easy mapping of the SPMI address space to shared memories or peripheral registers. A dedicated interface allows integration with application specific authentication logic, which can be reduced to just hardwiring the authentication response data.
CACHE-CTRL, The AHB Cache Controller Core
The CACHE-CTRL IP core is a flexible cache memory controller providing a 32-bit slave AHB processor interface and a 32-bit master AHB interface to the memory subsystem.
The cache controller core supports a four-way associative cache memory, and implements a Least Recently Used (LRU) replacement policy. The number of cache lines and the cache line width are configurable at synthesis time. The core only caches read accesses and invalidates the cached data if a write access to a cached memory location occurs.
Mapping the cache controller to any technology is straightforward, as the core does not require any special type of SRAM modules, only using standard, single-ported SRAMs. Furthermore, the design is scan-ready as it uses only rising-edge triggered flip-flops and contains no internal tri-states. Integration of the core is trouble-free, as the core uses standard 32-bit AHB interfaces, and supports clock gating.
The CACHE-CTRL core has been robustly verified and is silicon-proven.
T80251XC3 Tiny, Configurable, 16-bit Microcontroller Core
The T80251XC3 core implements a compact 16-bit microcontroller that executes the MCS®251 & MCS®51 instruction sets and includes a configurable range of features and integrated peripherals. The core’s advanced architectural design enables a high-performance 8051/80251-compatible MCU in a relatively small silicon footprint. The CPU itself (including the register files) is smaller than 13,000 gates, and can deliver 0.1455 DMIPS/MHz.
The T80251XC3 is extremely energy efficient, especially for applications that process 8- or 16-bit data. Its small footprint translates to very little power leakage, and its better performance than other 8-bit or 16-bit MCUs allows clocking at lower frequencies. Users can also adjust the core’s energy consumption to match the processing workload via dynamic frequency scaling and independent control of the CPU and peripherals clocks. Finally, the 80251 ISA’s complex addressing modes minimize the number of load/store operations, which typically comprise 20% or more of a RISC processor’s code. With denser code needing smaller firmware memory and fewer required memory accesses, the energy consumption of the MCU’s memory subsystem can be significantly less with the T80251XC3.
The core has a rich set of optional features and pre-integrated peripherals, allowing function, performance, and area to be balanced for each specific application. Software development is facilitated by a single-wire or JTAG debugging interface that operates seamlessly within the ARM® Keil® C251 integrated development environment. Inexpensive debug pods and a complete reference design board package are available.
T8051XC3 ULTRA-SMALL MICROCONTROLLER SOFT IP CORE
The T8051XC3 core implements one of the smallest-available 8-bit MCS®51-compatible microcontrollers. The core integrates an 8051 CPU with a serial communication controller, flexible timer/counter, multi-purpose I/O port, interrupt controller, and optionally with a debug unit supporting JTAG and Single-Wire interfaces. The MCU with all peripherals uses as little as 6.6K gates in an ASIC implementation.
The MCU executes some 8051 instructions in a single clock cycle, thus providing 0.1236 DMIPS/MHz (Dhrystone 2.1 benchmark score). Furthermore, the core can run at frequencies over 450 MHz on a 90nm technology, offering performance that is more than 300x that of the original 8051.
The T8051XC3 runs the legacy code of existing systems, but is also ready for highly productive new software development. This is facilitated through the on-chip debugging option, and debug pods that cooperate with the Keil µVision C51 and IAR Embedded Workbench for 8051 IDEs.
S80251XC3 Ultra Fast Microcontroller IP Core
The S80251XC3 is a synthesizable soft HDL core of a super-fast 16-bit 80C251-compatible microcontroller, backward compatible with the most popular 8-bit microcontroller, the 8051. It runs 69.7 times faster than the original 8051 chip (measured by Dhrystone benchmark), making it the highest performance MCS®51 instruction set compatible IP core available at the time of its release.
The new S80251XC3 uses a Harvard architecture with separate instruction and data buses, branch prediction, branch target caches, and stacking/unstacking speed-up features, and is even able to execute some instructions in parallel. With the rich set of peripherals and options, including timers and counters, buses and interfaces, the new core is an excellent choice as a sensor or peripheral subsystem controller in mobile, Internet of Things (IoT), and industrial systems, or as a main embedded processor in mixed-signal ICs for a variety of applications.
S8051XC3 Microcontroller Soft IP Core
The S8051XC3 is a synthesizable soft HDL core of a super fast 8-bit microcontroller compatible with the world’s most popular 8051 architecture. It offers the highest performance, low-energy and a configurable range of features and integrated peripherals.
At the time of its release, it is the fastest 8051-compatible 8-bit MCU ever designed. Running with a single clock per machine cycle, requiring an average of 1.5 to 1.8 machine cycles per instruction (depending on configuration), it delivers from 9.41 to 26.85 times the performance of the original 8051 at the same frequency (measured with Dhrystone 2.1 benchmark), without requiring an external arithmetic acceleration unit (such as an MDU).
Most of the extensions can be individually enabled or disabled from implementation, allowing to reduce the die size when top performance is not required. The core includes all typical 8051 peripherals like Timers, PWM, UART, SPI, I2C and extremely short latency interrupt system with extended priority structure.