{"id":211,"date":"2020-12-04T14:44:26","date_gmt":"2020-12-04T13:44:26","guid":{"rendered":"https:\/\/silesia-devices.com\/?page_id=211"},"modified":"2023-04-19T09:35:22","modified_gmt":"2023-04-19T09:35:22","slug":"public-announcements-ogloszenia-publiczne","status":"publish","type":"page","link":"https:\/\/silesia-devices.com\/index.php\/public-announcements-ogloszenia-publiczne\/","title":{"rendered":"Public Announcements \/ Og\u0142oszenia Publiczne"},"content":{"rendered":"\n

Biuro Projektowo-Us\u0142ugowe                                                  Katowice 17.12.2020
Silesia Devices Sp. z o.o.
ul. Ko\u015bciuszki 26\/7,
40-048 Katowice, Polska<\/p>\n\n\n\n

Information on the result of the tender procedure<\/strong><\/p>\n\n\n\n

As a result of the inquiry procedure of December 5th, 2020, for the purchase of virtual components (IP cores) of the MJPEG encoder and Ethernet controller for the project “Tell multiple stories with a single camera \u2013 leveraging AI and FPGAs for 4x real-time cinematography” co-financed in the Eurostars-2 competition as part of the EUREKA and European Union initiative, the tender submitted by CAST Inc., 11 Stonewall Ct., Woodcliff Lake, NJ 07677, USA was selected.<\/p>\n\n\n\n

Four proposals were received, and the selected offer was the only one that was fully comprehensive, especially in terms of the Ethernet controller requirements.<\/p>\n\n\n\n

Informacja o wyniku post\u0119powania ofertowego<\/strong><\/p>\n\n\n\n

W wyniku post\u0119powania dotycz\u0105cego zapytania ofertowego z dnia 5go grudnia 2020 na zakup komponent\u00f3w wirtualnych (IP cores) kodera MJPEG and kontrolera Ethernet do projektu \u201ePrzedstaw jednocze\u015bnie cztery sceny za pomoc\u0105 jednej kamery, u\u017cywaj\u0105c sztucznej inteligencji i uk\u0142ad\u00f3w FPGA\u201d wsp\u00f3\u0142finansowanego w konkursie Eurostars-2 w ramach inicjatywy EUREKA i Unii Europejskiej, wybrano ofert\u0119 z\u0142o\u017con\u0105 przez CAST Inc., 11 Stonewall Ct., Woodcliff Lake, NJ 07677, USA.<\/p>\n\n\n\n

Wp\u0142yn\u0119\u0142y 4 oferty, przy czym wybrana oferta jako jedyna by\u0142a w pe\u0142ni kompleksowa, szczeg\u00f3lnie pod k\u0105tem wymaga\u0144 dla kontrolera Ethernet.<\/p>\n\n\n\n

<\/p>\n\n\n\n

<\/p>\n\n\n\n

<\/p>\n\n\n\n

Request for Proposals
for MJPEG encoder and Ethernet Controller IP core netlists<\/span><\/strong><\/p>\n\n\n\n

Procuring entity<\/span><\/strong><\/td>Biuro Projektowo-Us\u0142ugowe Silesia Devices Sp. z o.o. ul. Ko\u015bciuszki 26\/7, 40-048 Katowice, Poland<\/span><\/td><\/tr>
Issue date<\/span><\/strong><\/td>December 5th<\/sup>, 2020<\/span><\/td><\/tr>
Proposal due date<\/span><\/strong><\/td>December 15th<\/sup>, 2020<\/span><\/td><\/tr>
Send proposals via email to<\/span><\/strong><\/td>jacek.tyminski@silesia-devices.com<\/a> (Jacek Tyminski)<\/span><\/td><\/tr>
Contact for RFP questions and communications<\/span><\/strong><\/td>General:<\/span> info@silesia-devices.com<\/a>
Formal information: Jacek Tyminski,<\/span> jacek.tyminski@silesia-devices.com<\/a>, +48 604 987 859 Technical Information: Maciej Pyka,<\/span> maciej.pyka@silesia-devices.com<\/a>, +48 604 987 849<\/span><\/td><\/tr>
Introduction<\/span><\/strong><\/td>Silesia Devices is an engineering company that deals with digital design services for ASIC \/ FPGA. It designs and sells IP cores of microcontrollers and peripherals for serial interface control and memory cache support during seven years of operation. At the same time, the company provides design services to various significant companies from the electronics industry.<\/span><\/td><\/tr>
Background<\/span><\/strong><\/td>Co-financed in the Eurostars-2 competition as part of the EUREKA and European Union initiative, in a consortium with two other European companies, Silesia Devices participates in the project “Tell multiple stories with a single camera – leveraging AI and FPGAs for 4x real-time cinematography”. As part of this project, Silesia Devices is responsible for designing, evaluating, and testing the hardware part of image processing. To optimize the project’s time and costs, the purchase of a license for virtual components (IP cores) of two controllers: MJPEG encoder and Ethernet controller, which are the subject of this RFP, was planned.<\/span><\/td><\/tr>
Order description<\/span><\/strong><\/td>1. The subject of this request are IP cores of the following modules:<\/strong><\/span>
a. MJPEG encoder allowing to compress a video stream with 1080p 60fps parameters in real-time on Xilinx Kintex7\/Ultrascale FPGA. The encoder must support bit-rate control, programmable quantization tables, and the following subsampling formats: 4:4:4, 4:2:0, and 4:2:2, <\/span>
b. a 1Gbps Ethernet controller supporting the following functionalities: simultaneous UDPI\/IP streaming of 4 compressed MJPEG streams, UDP\/IP encapsulation, DHCP (client), ICMP, IGMPv3 and unicast, ARP, and a network server module that enables support of a simple Application Programming Interface (API). <\/span>
2. Both controllers shall:<\/strong> <\/span>
a. be easily integrated with the Xilinx Microblaze processor via the AMBA AHB\/APB interface for control and configuration purposes, <\/span>
b. enable data streaming via the AXI interface, <\/span>
c. minimal CPU involvement, <\/span>
d. be covered by warranty and technical support for a minimum of one year from the date of purchase.<\/span><\/td><\/tr>
Deliverables<\/span><\/strong><\/td>1. Xilinx FPGA netlist.
2. User manual.
3. Verilog testbench.
4. Example design.<\/span><\/td><\/tr>
Delivery date<\/span><\/strong><\/td>December 31st<\/sup>, 2020<\/span><\/td><\/tr>
Offers evaluation criteria<\/span><\/strong><\/td>1. Offer must meet the requirements set out above.
2. Price criterion.
3. Complexity offer criterion. The offer may only be for one module (MJPEG encoder or Ethernet controller), but if the bidder proposes both modules at the total price equal to or less than the lowest total cost of purchasing both modules from two different bidders, then the entity supplying both modules wins.<\/span><\/td><\/tr>
Additional reservation<\/span><\/strong><\/td>1. The ordering party reserves the right to withdraw or cancel the RFP without giving reasons. <\/span>
2. The bidders will be informed about the competition results by email.<\/span><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

<\/p>\n\n\n\n

Zapytanie ofertowe
dotycz\u0105ce
komponent\u00f3w wirtualnych (IP cores) kodera MJPEG and kontrolera Ethernet<\/span><\/strong><\/p>\n\n\n\n

Zamawiaj\u0105cy<\/span><\/strong><\/td>Biuro Projektowo-Us\u0142ugowe Silesia Devices Sp. z o.o.<\/span>
ul. Ko\u015bciuszki 26\/7, 40-048 Katowice, Polska<\/span><\/td><\/tr>
Data wydania<\/span><\/strong><\/td>5 grudnia 2020<\/span><\/td><\/tr>
Termin sk\u0142adania ofert<\/span><\/strong><\/td>15 grudnia 2020<\/span><\/td><\/tr>
Sk\u0142adanie ofert do<\/span><\/strong><\/td>jacek.tyminski@silesia-devices.com<\/a> (Jacek Tyminski)<\/span><\/td><\/tr>
Kontakt w sprawie dodatkowych informacji:<\/span><\/strong><\/td>Og\u00f3lny:
info@silesia-devices.com
Sprawy formalne:
Jacek Tyminski, <\/span>jacek.tyminski@silesia-devices.com<\/a>, +48 604 987 859
Informacje techniczne:
Maciej Pyka,<\/span> maciej.pyka@silesia-devices.com<\/a>, +48 604 987 849<\/span><\/td><\/tr>
Wst\u0119p<\/span><\/strong><\/td>Silesia Devices jest firm\u0105 in\u017cyniersk\u0105 zajmuj\u0105c\u0105 si\u0119 uk\u0142adami cyfrowymi dla technologii ASIC i FPGA. Od siedmiu lat projektuje i sprzedaje komponenty wirtualne (IP cores) mikrokontroler\u00f3w oraz peryferii do sterowania interfejs\u00f3w szeregowych i pami\u0119ci cache. Jednocze\u015bnie, \u015bwiadczy us\u0142ugi projektowe r\u00f3\u017cnym znacz\u0105cym przedsi\u0119biorstwom z bran\u017cy elektronicznej<\/span><\/td><\/tr>
Kontekst<\/span><\/strong><\/td>Wsp\u00f3\u0142finansowana w konkursie Eurostars-2 w ramach inicjatywy EUREKA i Unii Europejskiej, w konsorcjum z dwoma innymi europejskimi przedsi\u0119biorstwami, Silesia Devices bierze udzia\u0142 w projekcie \u201cPrzedstaw jednocze\u015bnie cztery sceny za pomoc\u0105 jednej kamery, u\u017cywaj\u0105c sztucznej inteligencji i uk\u0142ad\u00f3w FPGA.\u201d W ramach tego projektu Silesia Devices jest odpowiedzialna za zaprojektowanie, ewaluacj\u0119 i testowanie cz\u0119\u015bci sprz\u0119towej przetwarzania obrazu. W celu zoptymalizowania czasu i koszt\u00f3w projektu zaplanowany zosta\u0142 zakup licencji na komponenty wirtualne (IP cores) dw\u00f3ch kontroler\u00f3w: kodera MJPEG i kontrolera Ethernet, kt\u00f3re s\u0105 przedmiotem tego zapytania.<\/span><\/td><\/tr>
Opis zam\u00f3wienia<\/span><\/strong><\/td>1. Przedmiotem zam\u00f3wienia ofertowego s\u0105 komponenty wirtualne (IP cores) nast\u0119puj\u0105cych modu\u0142\u00f3w:<\/strong> <\/span>
a. koder MJPEG umo\u017cliwiaj\u0105cy kompresj\u0119 strumienia video o parametrach 1080p 60fps w czasie rzeczywistym w uk\u0142adzie FPGA Kintex7\/Ultrascale. Koder musi obs\u0142ugiwa\u0107 sterowanie przep\u0142ywno\u015bci\u0105, programowalne tabele kwantyzacji i nast\u0119puj\u0105ce formaty pr\u00f3bkowania chrominancji:: 4: 4: 4, 4: 2: 0 i 4: 2: 2, <\/span>
b. kontroler Ethernet 1Gbps obs\u0142uguj\u0105cy nast\u0119puj\u0105ce funkcjonalno\u015bci: jednoczesne przesy\u0142anie strumieniowe UDPI \/ IP 4 skompresowanych strumieni MJPEG, enkapsulacja UDP \/ IP, DHCP (klient), ICMP, IGMPv3 i unicast, ARP oraz modu\u0142 serwera sieciowego, kt\u00f3ry umo\u017cliwia obs\u0142ug\u0119 prostego interfejsu programowania aplikacji (API).<\/span>
2. Oba modu\u0142y powinny:<\/strong> <\/span>
a. umo\u017cliwia\u0107 \u0142atw\u0105 integracj\u0119 z procesorem Xilinx Microblaze za po\u015brednictwem interfejsu AMBA AHB \/ APB do cel\u00f3w sterowania i konfiguracji, <\/span>
b. umo\u017cliwia\u0107 przesy\u0142anie danych przez interfejs AXI, <\/span>
c. minimalne anga\u017cowa\u0107 procesor, <\/span>
d. by\u0107 obj\u0119te gwarancj\u0105 i wsparciem technicznym przez co najmniej rok od daty zakupu.<\/span><\/td><\/tr>
Elementy dostawy<\/span><\/strong><\/td>1. Netlista dla uk\u0142adu FPGA firmy Xilinx. <\/span>
2. Instrukcja obs\u0142ugi. <\/span>
3. \u015arodowisko testowe w j\u0119zyku Verilog.
4. Przyk\u0142adowy projekt.<\/span><\/td><\/tr>
Termin dostawy<\/span><\/strong><\/td>31 grudnia 2020<\/span><\/td><\/tr>
Kryteria oceny ofert<\/span><\/strong><\/td>1. Oferta musi spe\u0142nia\u0107 wszystkie wymogi wymienione powy\u017cej. <\/span>
2. Kryterium cenowe. <\/span>
3. Kryterium kompleksowo\u015bci oferty. Oferta mo\u017ce dotyczy\u0107 tylko jednego modu\u0142u (kodera MPEG albo kontrolera Ethernet), ale pierwsze\u0144stwo ma oferta obu kontroler\u00f3w je\u015bli jej kwota jest r\u00f3wna lub ni\u017csza najni\u017cszemu kosztowi zakupu obu modu\u0142\u00f3w u dw\u00f3ch r\u00f3\u017cnych dostawc\u00f3w.<\/span><\/td><\/tr>
Zastrze\u017cenia<\/span><\/strong><\/td>1. Zamawiaj\u0105cy zastrzega sobie prawo do odst\u0105pienia lub anulowania zapytania ofertowego bez podania przyczyn. <\/span>
2. O wyniku post\u0119powania oferenci b\u0119d\u0105 powiadomieni drog\u0105 elektroniczn\u0105.<\/span><\/td><\/tr><\/tbody><\/table><\/figure>\n","protected":false},"excerpt":{"rendered":"

Biuro Projektowo-Us\u0142ugowe                                                  Katowice 17.12.2020Silesia Devices Sp. z o.o.ul. Ko\u015bciuszki 26\/7,40-048 Katowice, Polska Information on the result of the tender procedure As a result of the inquiry procedure of December 5th, 2020, for the purchase of virtual components (IP cores) of the MJPEG encoder and Ethernet controller for the project “Tell multiple […]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"ocean_post_layout":"full-screen","ocean_both_sidebars_style":"","ocean_both_sidebars_content_width":0,"ocean_both_sidebars_sidebars_width":0,"ocean_sidebar":"0","ocean_second_sidebar":"0","ocean_disable_margins":"enable","ocean_add_body_class":"","ocean_shortcode_before_top_bar":"","ocean_shortcode_after_top_bar":"","ocean_shortcode_before_header":"","ocean_shortcode_after_header":"","ocean_has_shortcode":"","ocean_shortcode_after_title":"","ocean_shortcode_before_footer_widgets":"","ocean_shortcode_after_footer_widgets":"","ocean_shortcode_before_footer_bottom":"","ocean_shortcode_after_footer_bottom":"","ocean_display_top_bar":"off","ocean_display_header":"default","ocean_header_style":"","ocean_center_header_left_menu":"0","ocean_custom_header_template":"0","ocean_custom_logo":0,"ocean_custom_retina_logo":0,"ocean_custom_logo_max_width":0,"ocean_custom_logo_tablet_max_width":0,"ocean_custom_logo_mobile_max_width":0,"ocean_custom_logo_max_height":0,"ocean_custom_logo_tablet_max_height":0,"ocean_custom_logo_mobile_max_height":0,"ocean_header_custom_menu":"0","ocean_menu_typo_font_family":"0","ocean_menu_typo_font_subset":"","ocean_menu_typo_font_size":0,"ocean_menu_typo_font_size_tablet":0,"ocean_menu_typo_font_size_mobile":0,"ocean_menu_typo_font_size_unit":"px","ocean_menu_typo_font_weight":"","ocean_menu_typo_font_weight_tablet":"","ocean_menu_typo_font_weight_mobile":"","ocean_menu_typo_transform":"","ocean_menu_typo_transform_tablet":"","ocean_menu_typo_transform_mobile":"","ocean_menu_typo_line_height":0,"ocean_menu_typo_line_height_tablet":0,"ocean_menu_typo_line_height_mobile":0,"ocean_menu_typo_line_height_unit":"","ocean_menu_typo_spacing":0,"ocean_menu_typo_spacing_tablet":0,"ocean_menu_typo_spacing_mobile":0,"ocean_menu_typo_spacing_unit":"","ocean_menu_link_color":"","ocean_menu_link_color_hover":"","ocean_menu_link_color_active":"","ocean_menu_link_background":"","ocean_menu_link_hover_background":"","ocean_menu_link_active_background":"","ocean_menu_social_links_bg":"","ocean_menu_social_hover_links_bg":"","ocean_menu_social_links_color":"","ocean_menu_social_hover_links_color":"","ocean_disable_title":"on","ocean_disable_heading":"default","ocean_post_title":"","ocean_post_subheading":"","ocean_post_title_style":"","ocean_post_title_background_color":"","ocean_post_title_background":0,"ocean_post_title_bg_image_position":"","ocean_post_title_bg_image_attachment":"","ocean_post_title_bg_image_repeat":"","ocean_post_title_bg_image_size":"","ocean_post_title_height":0,"ocean_post_title_bg_overlay":0.5,"ocean_post_title_bg_overlay_color":"","ocean_disable_breadcrumbs":"default","ocean_breadcrumbs_color":"","ocean_breadcrumbs_separator_color":"","ocean_breadcrumbs_links_color":"","ocean_breadcrumbs_links_hover_color":"","ocean_display_footer_widgets":"off","ocean_display_footer_bottom":"off","ocean_custom_footer_template":"0","footnotes":""},"class_list":["post-211","page","type-page","status-publish","hentry","entry"],"_links":{"self":[{"href":"https:\/\/silesia-devices.com\/index.php\/wp-json\/wp\/v2\/pages\/211","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/silesia-devices.com\/index.php\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/silesia-devices.com\/index.php\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/silesia-devices.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/silesia-devices.com\/index.php\/wp-json\/wp\/v2\/comments?post=211"}],"version-history":[{"count":1,"href":"https:\/\/silesia-devices.com\/index.php\/wp-json\/wp\/v2\/pages\/211\/revisions"}],"predecessor-version":[{"id":226,"href":"https:\/\/silesia-devices.com\/index.php\/wp-json\/wp\/v2\/pages\/211\/revisions\/226"}],"wp:attachment":[{"href":"https:\/\/silesia-devices.com\/index.php\/wp-json\/wp\/v2\/media?parent=211"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}